patch-2.4.4 linux/include/asm-sh/irq.h

• Lines: 284
• Date: Wed Apr 11 21:24:52 2001
• Orig file: v2.4.3/linux/include/asm-sh/irq.h
• Orig date: Mon Oct 2 11:57:34 2000

diff -u --recursive --new-file v2.4.3/linux/include/asm-sh/irq.h linux/include/asm-sh/irq.h
@@ -12,6 +12,7 @@
 
 #include <linux/config.h>
 #include <asm/machvec.h>
+#include <asm/ptrace.h>		/* for pt_regs */
 
 #if defined(__sh3__)
 #define INTC_IPRA  	0xfffffee2UL
@@ -32,12 +33,24 @@
 #define RTC_IPR_POS	 0
 #define RTC_PRIORITY	TIMER_PRIORITY
 
+#define DMTE0_IRQ	34
+#define DMTE1_IRQ	35
+#define DMTE2_IRQ	36
+#define DMTE3_IRQ	37
+#define DMAE_IRQ	38
+#define DMA_IPR_ADDR	INTC_IPRC
+#define DMA_IPR_POS	2
+#define DMA_PRIORITY	7
+
+#if defined (CONFIG_CPU_SUBTYPE_SH7707) || defined (CONFIG_CPU_SUBTYPE_SH7708) || \
+    defined (CONFIG_CPU_SUBTYPE_SH7709) || defined (CONFIG_CPU_SUBTYPE_SH7750)
 #define SCI_ERI_IRQ	23
 #define SCI_RXI_IRQ	24
 #define SCI_TXI_IRQ	25
 #define SCI_IPR_ADDR	INTC_IPRB
 #define SCI_IPR_POS	1
 #define SCI_PRIORITY	3
+#endif
 
 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
 #define SCIF_ERI_IRQ	56
@@ -55,7 +68,7 @@
 #define IRDA_IPR_ADDR	INTC_IPRE
 #define IRDA_IPR_POS	2
 #define IRDA_PRIORITY	3
-#elif defined(CONFIG_CPU_SUBTYPE_SH7750)
+#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_ST40STB1)
 #define SCIF_ERI_IRQ	40
 #define SCIF_RXI_IRQ	41
 #define SCIF_BRI_IRQ	42
@@ -63,38 +76,87 @@
 #define SCIF_IPR_ADDR	INTC_IPRC
 #define SCIF_IPR_POS	1
 #define SCIF_PRIORITY	3
+#if defined(CONFIG_CPU_SUBTYPE_ST40STB1)
+#define SCIF1_ERI_IRQ	23
+#define SCIF1_RXI_IRQ	24
+#define SCIF1_BRI_IRQ	25
+#define SCIF1_TXI_IRQ	26
+#define SCIF1_IPR_ADDR	INTC_IPRB
+#define SCIF1_IPR_POS	1
+#define SCIF1_PRIORITY	3
+#endif
 #endif
 
-#ifdef CONFIG_SH_GENERIC
-/* In a generic kernel, NR_IRQS is an upper bound, and we should use
- * ACTUAL_NR_IRQS (which uses the machine vector) to get the correct value.
+/* NR_IRQS is made from three components:
+ *   1. ONCHIP_NR_IRQS - number of IRLS + on-chip peripherial modules
+ *   2. PINT_NR_IRQS   - number of PINT interrupts
+ *   3. OFFCHIP_NR_IRQS - numbe of IRQs from off-chip peripherial modules
  */
-#define NR_IRQS 80
-#define ACTUAL_NR_IRQS (sh_mv.mv_nr_irqs)
+
+/* 1. ONCHIP_NR_IRQS */
+#ifdef CONFIG_SH_GENERIC
+# define ONCHIP_NR_IRQS 89
 #else
-#if defined(__SH4__)
-/*
- * 48 = 32+16
- *
- * 32 for on chip support modules.
- * 16 for external interrupts.
- *
- */
-#define NR_IRQS	48
-#elif defined(CONFIG_CPU_SUBTYPE_SH7707)
-#define NR_IRQS 64
-#elif defined(CONFIG_CPU_SUBTYPE_SH7708)
-#define NR_IRQS 32
-#elif defined(CONFIG_CPU_SUBTYPE_SH7709)
-#ifdef CONFIG_HD64461
-#define NR_IRQS 80		/* HD64461_IRQBASE+16, see hd64461.h */
+# if defined(CONFIG_CPU_SUBTYPE_SH7707)
+#  define ONCHIP_NR_IRQS 64
+#  define PINT_NR_IRQS   16
+# elif defined(CONFIG_CPU_SUBTYPE_SH7708)
+#  define ONCHIP_NR_IRQS 32
+# elif defined(CONFIG_CPU_SUBTYPE_SH7709)
+#  define ONCHIP_NR_IRQS 64	// Actually 61
+#  define PINT_NR_IRQS   16
+# elif defined(CONFIG_CPU_SUBTYPE_SH7750)
+#  define ONCHIP_NR_IRQS 48	// Actually 44
+# elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
+#  define ONCHIP_NR_IRQS 89
+# endif
+#endif
+
+/* 2. PINT_NR_IRQS */
+#ifdef CONFIG_SH_GENERIC
+# define PINT_NR_IRQS 16
 #else
-#define NR_IRQS 61
+# ifndef PINT_NR_IRQS
+#  define PINT_NR_IRQS 0
+# endif
 #endif
+
+#if PINT_NR_IRQS > 0
+# define PINT_IRQ_BASE  ONCHIP_NR_IRQS
 #endif
-#define ACTUAL_NR_IRQS NR_IRQS
+
+/* 3. OFFCHIP_NR_IRQS */
+#ifdef CONFIG_SH_GENERIC
+# define OFFCHIP_NR_IRQS 16
+#else
+# if defined(CONFIG_HD64461)
+#  define OFFCHIP_NR_IRQS 16
+# elif defined(CONFIG_HD64465)
+#  define OFFCHIP_NR_IRQS 16
+# elif defined (CONFIG_SH_EC3104)
+#  define OFFCHIP_NR_IRQS 16
+# else
+#  define OFFCHIP_NR_IRQS 0
+# endif
 #endif
 
+#if OFFCHIP_NR_IRQS > 0
+# define OFFCHIP_IRQ_BASE (ONCHIP_NR_IRQS + PINT_NR_IRQS)
+#endif
+
+/* NR_IRQS. 1+2+3 */
+#define NR_IRQS (ONCHIP_NR_IRQS + PINT_NR_IRQS + OFFCHIP_NR_IRQS)
+
+/* In a generic kernel, NR_IRQS is an upper bound, and we should use
+ * ACTUAL_NR_IRQS (which uses the machine vector) to get the correct value.
+ */
+#ifdef CONFIG_SH_GENERIC
+# define ACTUAL_NR_IRQS (sh_mv.mv_nr_irqs)
+#else
+# define ACTUAL_NR_IRQS NR_IRQS
+#endif
+
+
 extern void disable_irq(unsigned int);
 extern void disable_irq_nosync(unsigned int);
 extern void enable_irq(unsigned int);
@@ -123,6 +185,15 @@
 #define INTC_IPRF	0xa400001cUL
 #endif
 
+#define PORT_PACR	0xa4000100UL
+#define PORT_PBCR	0xa4000102UL
+#define PORT_PCCR	0xa4000104UL
+#define PORT_PFCR	0xa400010aUL
+#define PORT_PADR  	0xa4000120UL
+#define PORT_PBDR  	0xa4000122UL
+#define PORT_PCDR  	0xa4000124UL
+#define PORT_PFDR  	0xa400012aUL
+
 #define IRQ0_IRQ	32
 #define IRQ1_IRQ	33
 #define IRQ2_IRQ	34
@@ -130,19 +201,19 @@
 #define IRQ4_IRQ	36
 #define IRQ5_IRQ	37
 
-#define IRQ0_IRP_ADDR	INTC_IPRC
-#define IRQ1_IRP_ADDR	INTC_IPRC
-#define IRQ2_IRP_ADDR	INTC_IPRC
-#define IRQ3_IRP_ADDR	INTC_IPRC
-#define IRQ4_IRP_ADDR	INTC_IPRD
-#define IRQ5_IRP_ADDR	INTC_IPRD
-
-#define IRQ0_IRP_POS	0
-#define IRQ1_IRP_POS	1
-#define IRQ2_IRP_POS	2
-#define IRQ3_IRP_POS	3
-#define IRQ4_IRP_POS	0
-#define IRQ5_IRP_POS	1
+#define IRQ0_IPR_ADDR	INTC_IPRC
+#define IRQ1_IPR_ADDR	INTC_IPRC
+#define IRQ2_IPR_ADDR	INTC_IPRC
+#define IRQ3_IPR_ADDR	INTC_IPRC
+#define IRQ4_IPR_ADDR	INTC_IPRD
+#define IRQ5_IPR_ADDR	INTC_IPRD
+
+#define IRQ0_IPR_POS	0
+#define IRQ1_IPR_POS	1
+#define IRQ2_IPR_POS	2
+#define IRQ3_IPR_POS	3
+#define IRQ4_IPR_POS	0
+#define IRQ5_IPR_POS	1
 
 #define IRQ0_PRIORITY	1
 #define IRQ1_PRIORITY	1
@@ -150,21 +221,77 @@
 #define IRQ3_PRIORITY	1
 #define IRQ4_PRIORITY	1
 #define IRQ5_PRIORITY	1
-#endif
 
-extern int hd64461_irq_demux(int irq);
+#define PINT0_IRQ	40
+#define PINT8_IRQ	41
+
+#define PINT0_IPR_ADDR	INTC_IPRD
+#define PINT8_IPR_ADDR	INTC_IPRD
+
+#define PINT0_IPR_POS	3
+#define PINT8_IPR_POS	2
+#define PINT0_PRIORITY	2
+#define PINT8_PRIORITY	2
 
+extern int ipr_irq_demux(int irq);
+#define __irq_demux(irq) ipr_irq_demux(irq)
+
+#else
+#define __irq_demux(irq) irq
+#endif /* CONFIG_CPU_SUBTYPE_SH7707 || CONFIG_CPU_SUBTYPE_SH7709 */
+
+#ifdef CONFIG_CPU_SUBTYPE_ST40STB1
+#define INTC2_FIRST_IRQ 64
+#define NR_INTC2_IRQS 25
+ 
+#define INTC2_BASE0 0xfe080000
+#define INTC2_INTC2MODE  (INTC2_BASE0+0x80)
+ 
+#define INTC2_INTPRI_OFFSET	0x00
+#define INTC2_INTREQ_OFFSET	0x20
+#define INTC2_INTMSK_OFFSET	0x40
+#define INTC2_INTMSKCLR_OFFSET	0x60
+ 
+extern void make_intc2_irq(unsigned int irq,unsigned int addr,
+                           unsigned int group,int pos,int priority);
+ 
+#endif                                                                        
+       
 #ifdef CONFIG_SH_GENERIC
+
 extern __inline__ int irq_demux(int irq) {
 	if (sh_mv.mv_irq_demux) {
 		irq = sh_mv.mv_irq_demux(irq);
 	}
-	return irq;
+	return __irq_demux(irq);
 }
+
 #elif defined(CONFIG_HD64461)
+
+extern int hd64461_irq_demux(int irq);
 #define irq_demux(irq) hd64461_irq_demux(irq)
+
+#elif defined(CONFIG_HD64465)
+
+extern int hd64465_irq_demux(int irq);
+#define irq_demux(irq) hd64465_irq_demux(irq)
+
+#elif defined(CONFIG_SH_EC3104)
+
+extern int ec3104_irq_demux(int irq);
+#define irq_demux ec3104_irq_demux
+
+#elif defined(CONFIG_SH_CAT68701)
+
+extern int cat68701_irq_demux(int irq);
+#define irq_demux cat68701_irq_demux
+
 #else
-#define irq_demux(irq) irq
+
+#define irq_demux(irq) __irq_demux(irq)
+
 #endif
+
+
 
 #endif /* __ASM_SH_IRQ_H */